Llano Architecture in detail
As explained above, within an Llano APU there are up to 4 x86 processor core, and up to 400 stream processors, divided into SIMD Engine of 80 stream processors each. CPU and GPU share access to the DDR3 memory type through a high-performance integrated memory controller. The integrated controller has been improved in the management of data transfers, prefetching algorithms and in the maximum RAM frequency supported, which arrives at 1866 MHz and the presence of a 128-bit dual-channel bus was confirmed.
The APU also features a type 3 UVD video decoder which has already been extensively discussed in other reviews, a PCI Express 2.0 x16 controller, and the management of the display via HDMI 1.4a, DVI and Display Port. The APU is also connected via the Unified Media Interface bus to the Hudson Fusion Controller Hub (FCH) who is in charge of management of peripheral I/O.
Among the most interesting features of the D3 Hudson chipset we find support to next generation standards with up to 6 6Gb/s SATA ports (with the possibility of RAID 0 and 1) and up to 4 USB 3.0. It also manages 10 USB 2.0, 4 PCI Express x1, HD Audio chip and PCI interfaces. We will see in detail the features of this chipset.
Regarding the details of the Llano APU x86 Core there are no easily visible news. The basic architecture is the "Stars" type core, but with some improvements that result in an average increase of 6% compared to the Propus core IPC: the doubling of L2 cache per core, now 1MB, and the use of 8 transistors cells only for L1 data cache, faster, more reliable and able to operate at a lower voltage and therefore less power hungry, the increase of the various internal queues (of the instruction control unit, of the integer, floating point and memory instructions) the improvement of the integer multiplier and the integration of a very efficient integer divider, the increase of Translation Lookaside Buffers for the virtual memory management and improvement of the memory controller, in particular in transfer rate and prefetching algorithms. In addition TurboCore technology has been upgraded to version 2.0, with a better estimate of the instantaneous power absorbed and the precise balance of power between GPU and CPU.
We can not expect great performance at a computational level from the Llano CPU Core, because we start from the performance of the Propus core. However, the presence of a very large number of Stream Processors on the paper makes an Llano APU the most powerful APU ever made in terms of GFLOPS. In addition, the zero copy and Pin In Place technologies, offer a substantial improvement in the memory performance, compared to an IGP and also compared to a discrete graphics card. These technologies allow the GPU to directly use the data in main memory, without having to go through the PCI Express bus, as in the past. The power offered by AMD SIMD can be exploited, however, only by those applications that take advantage of GPU acceleration. To that end, AMD is working closely with many software companies, to allow users to exploit this untapped potential in an efficient manner.
